FPGA Senior Engineer

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You are our digital circuits professional. You will work with the technical team to design and implement high-performance digital circuits on FPGA or ASIC, and be responsible for the entire FPGA build flow from RTL code to verification and timing closure. You are also expected to bring-up, test and verify the final hardware product, together with the product team.

Responsibilities

  • Design and implementation of high-performance digital circuits on FPGA or ASIC
  • Prepare microarchitecture design based on system specifications and architecture documentation
  • Follow through the entire FPGA build flow to perform the various front-end tasks such as RTL coding, synthesis, test and verification and timing closure
  • Work closely with hardware design engineers to define I/O interfaces for FPGA and ASIC hardware systems
  • Work closely with software design engineers to define register mappings for SoC systems
  • Prepare design documents and test reports
  • Work closely as a team to perform bring-up, test and verification on final hardware product

Requirements

  • At least 4 years of relevant experience in FPGA hardware such as Altera, Xilinx or Lattice
  • Proficient in at least one RTL language such as VHDL or Verilog
  • Familiar with FPGA build flow from design entry to synthesis, place and route, timing constraints and timing closure
  • Familiar with development, integration or testing of high speed data interfaces such as 1/10G Ethernet and PCIe
  • Hands-on experience in FPGA debugging tools such as Vivado ILA and Quartus SignalTap
  • Good problem solving and failure analysis skills
  • Experience in board bring-up and hardware debugging
  • Experience in using source control tools such as Git strongly preferred
  • Experience in developing UVM test-benches to perform functional simulations on module/system level RTL designs is desirable
  • Familiar with programming languages like C/C++ and scripting languages like Python/Tcl
  • Experience in SoC hardware development is a strong advantage
  • Knowledge and familiarity in ASIC related front-end tasks such as synthesis, timing analysis and logic equivalence check will be advantageous
  • Provide customer support in resolving functional or performance issues

Interested applicants, please click on "Apply Now" to send in a copy of your resume.

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Offices

Operating Office: 30 Sin Ming Lane, Midview City, Singapore 573953, Republic of Singapore. Tel: +65 69331800, Fax: +65 66845142

Corporate Office: 28 Sin Ming Lane, #06-133 Midview City, Singapore 573972, Republic of Singapore. Tel: +65 69331800, Fax: +65 66845142

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